This invention relates to high speed data acquisition, and more particularly to a method and apparatus for generating sample and hold signals for a high speed signal acquisition system that have very short delay intervals between the sample-to-hold transitions of successive signals.
U.S. Pat. No. 5,144,525 to Saxe et al. for an "Analog Acquisition System Including a High Speed Timing Generator", hereby incorporated by reference, describes an analog signal acquisition system that includes an array of cells for capturing and storing an analog signal. This analog signal acquisition system is faster than another high speed, fast-in slow-out (FISO) acquisition system described in U.S. Pat. No. 4,271,488 to Saxe for a "High-Speed Acquisition System Employing an Analog Memory Matrix", hereby incorporated by reference.
In U.S. Pat. No. 5,144,525, each cell in the array is selected sequentially for sampling at a very rapid rate. Rows within this array of cells are selected by slow timing signals generated by a slow shift register, while individual cells within each row are selected by fast sample and hold signals, generated in a variety of alternative ways.
One of the methods of generating rapidly occurring hold signals that is discussed in the U.S. Pat. No. 5,144,525 (in connection with FIG. 3) is a tapped delay line created by the propagation of a strobe signal through a series of buffer amplifiers. Since each buffer amplifier contains two inverting amplifiers, this approach produces hold signals that are separated in time by two inverter amplifier delay intervals. The time between hold signals can be reduced to a single amplifier delay interval by substituting inverting amplifiers for the buffer amplifiers, as is described in connection with FIG. 5 of the U.S. Pat. No. 5,144,525. Both of these methods are limited by the inherent minimum propagation time of the inverting amplifiers.
Yet another approach for generating a series of fast sequential hold signals that is discussed in the U.S. Pat. No. 5,144,525 (in connection with FIG. 6) is to use a number of buffer amplifiers in parallel, with each buffer amplifier having a different propagation delay as a result of variations in the value of internal resistances or other parameters between successive buffer amplifiers. While this method can produce timing variations that are less than a single amplifier delay, accurately controlling the propagation times to obtain equal time differences between successive amplifiers is very difficult.
Still another approach that is discussed in the U.S. Pat. No. 5,144,525 (in connection with FIG. 7) entails sending a strobe signal through a series of R-C networks, with the output of each network triggering a Schmitt trigger circuit to produce a hold signal as the strobe signal decays below an input threshold level of the Schmitt trigger. It is also difficult to produce even time intervals between successive hold signals using this method because resistors and capacitors with tight tolerances are difficult to achieve within an integrated circuit.
A final approach that is described in the U.S. Pat. No. 5,144,525 (in connection with FIGS. 9 and 9A) is the use of a ring oscillator as a tapped delay line. The minimum delays attainable through the use of this method are limited to the propagation time of a single inverter amplifier.
As is described in the U.S. Pat. No. 5,144,525, a complicating factor in the architecture of a high speed timing generator is the requirement that the signal input be sampled as uniformly as possible throughout the entire acquisition period. This means that the interval between sampling the last element in one row and the first element in the next row should exactly equal the interval between sampling adjacent elements within the same row. This in turn means that the sum of the high speed sample and hold signal intervals has to be equal to exactly one period of the clock that produces the low speed timing signals from the shift register.
To explain how this requirement may be satisfied, a considerable portion of the U.S. Pat. No. 5,144,525 is devoted to detecting coincidence between the input to the tapped delay means and its last output, and to methods for adjusting the delay through individual buffer amplifiers to alter the cumulative timing of the fast sample and hold signal generator to create such a coincidence relationship.
Although a variety of methods for generating sample and hold signal sample-to-hold transitions that are closely and evenly spaced in time are disclosed in the U.S. Pat. No. 5,144,525 even the fastest and most adjustable of these methods have limitations in their speed and adjustability that it would be desirable to improve upon.